In a multi-level Flash device the pages are separated by n-levels, corresponding to the number of bits stored per cell. FIG. 1 is a read threshold voltage distribution that demonstrates, for a 3 bits per cell Flash memory, how most significant bit/central significant bit and least significant bit (MSB/CSB/LSB) pages can be read (other mappings are also possible). This figure illustrates eight read threshold distribution lobes 11-18, MSB read threshold 24, two CSB read thresholds 22 and 26 and four LSB read thresholds 21, 23, 25 and 27.
As may be noticed from the figure, for reading an MSB page, only a single read threshold comparison (comparison to MSB read threshold 24) should be performed. For reading a CSB page, two CSB read thresholds 22 and 26 are to be used in order to determine the bit value of every CSB associated cell. For LSB pages the bit-values are determined using the four LSB read thresholds 21, 23, 25 AND 27.
In FIG. 1, the voltage level distributions per level are non-overlapping, however this is only schematic, and in practical cases the distributions may overlap. The reason for overlapping may be intentional for obtaining high programming speed, due to the retention effect, or due to cycling effect.
For floating gate devices, an “old” page, may introduce greater overlap between lobes than a new page, since after many program/erase (P/E) cycles there is accumulated trap charge, which is de-trapped over time. After a long duration, every lobe may have a larger standard deviation (std) and may have a different mean location. These affects are also known as retention. These are just two examples for overlapping distributions. There may be many more, such as read disturbs, or programming disturbs, etc.
As an example, we may consider a NAND FLASH array. The NAND FLASH array includes rows and columns (strings). During a read operation, an entire row/page is read from the NAND FLASH array. This is done by applying a bias voltage (or pass voltage) to all rows not being read and a reference read threshold voltage to the row we wish to read. Per each column of the NAND flash memory array one flash memory cell is read (the flash memory cell that belongs to the selected row) while the other flash memory cells are “open” due to the provision of the bias voltage.
The bias voltage allows the FLASH transistors to fully conduct. The cells lying on the row being read will conduct only if the read threshold voltage is sufficiently high to overcome the trapped change in the floating gate. At the bottom of each string there is a comparator which measures the current and outputs either a “1” or a “0” depending whether the current through that string passed a certain read threshold.
An MSB page is read by setting the MSB read threshold 24 between the fourth and fifth lobes 144 and 15. All lobes above the MSB read threshold 24 (lobes 15-18) will be read as “0”s and all lobes below that MSB read threshold 24 (lobes 11-14) will be read as “1”s.
As mentioned above, to read a CSB page two CSB read threshold 22 and 26 are used. Lobes 11 and 12 that are bellow the first CSB read threshold 22 and lobes 17 and 18 that are above the second CSB read threshold 26 will be read as “1”s. Lobes 13-16 that are between the two CSB read thresholds 22 and 26 will be read as “0”s. Similarly, the LSB pages are read by applying the four LSB read thresholds so that lobes 11, 14, 15 and 18 will be read as “1” and lobes 12-13 and 16-17 will be read as “1”.
It is noted that each lobe represents a set of MSB, CSB and LSB read values. Each flash memory cell of the 3 bpc flash memory cell stores such a set of values.
Those of skill in the art will appreciate that following retention, the positions of the lobes shift and they become wider. If during a read operation the same detection levels are used as just following programming, it is most likely that a considerable amount of read errors would occur. To overcome this problem, the read thresholds are modified as the block ages in order to minimize the number of read errors.
There is a growing need to find actual read thresholds to be applied during actual read attempts that will reduce the amount of read errors.